发明名称 |
Semiconductor arrangement manufacturing method, involves partially optimizing deceleration oxide and scattering oxide such that photons are raised to surface of guard ring and silicide is limited in guard ring area |
摘要 |
<p>The method involves partially optimizing deceleration oxide (41) and scattering oxide before producing surface-proximate areas with two different types of dopants such that photons are raised to a surface of a guard ring and silicide is limited in a guard ring area. A doped epitaxial layer is applied at a highly doped substrate, where the epitaxial layer and the substrate are doped with similar dopants. Thickness of a protective and brake oxide layer of a schottky diode of a semiconductor arrangement is set as 50 nanometers for implantation energy of 150 kilo electron volt.</p> |
申请公布号 |
DE102009056603(A1) |
申请公布日期 |
2011.06.09 |
申请号 |
DE20091056603 |
申请日期 |
2009.12.02 |
申请人 |
ERIS TECHNOLOGY CORP. |
发明人 |
RESCHKE, MICHAEL;HILLEMANN, HANS-JUERGEN;GUENTHER, KLAUS |
分类号 |
H01L21/329;H01L21/265;H01L29/872 |
主分类号 |
H01L21/329 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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