| 摘要 |
<p>First data latches (30a, 30b) having a number of bits equal to the page length are provided in the stage following sense amplifiers (20a, 20b) and are controlled so as to always hold the same data as that in the sense amplifiers. Upon initiation of CAS access, data is transferred from the first data latches (30a, 30b) to an error detection/correction circuit (40), and error correction and parity generation are performed in a pipelined manner to reduce the CAS access time and CAS cycle time.</p> |
