| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of suppressing a decrease in operation speed. <P>SOLUTION: The semiconductor device includes a silicon substrate 5 containing an MOS transistor 9, a multilayer wiring layer which is formed on the silicon substrate 5 with a plurality of wiring layers comprising a wiring and an insulting film, and a capacitance element 90 which is embedded in the multilayer wiring layer and contains a lower electrode (lower electrode film 91), a capacitance insulating film 92, and an upper electrode (upper electrode film 93) to constitute a memory element. Between the capacitance element 90 and the MOS transistor 9, at least one layer of damascene copper wiring (second layer wiring 25) is formed. The upper surface of one wiring (second layer wiring 25) and the lower surface of the capacitance element 90 are almost on the same plane. At least one layer of copper wiring (plate line wiring 99) is formed on the capacitance element 90. <P>COPYRIGHT: (C)2011,JPO&INPIT</p> |
