| 摘要 |
PURPOSE: A delay locked loop circuit is provided to perform delay locked without increasing the number of delay line by comparing a reference clock with a negative reference clock to perform delay locked. CONSTITUTION: A buffering part(40) buffers an external clock. A divider(41) divides the output clock of the buffering part into two. The divider generates a positive reference clock. A first phase comparison unit(42) compares a positive clock with the phase of a feedback clock. The first phase comparison unit outputs a first phase comparison signal. A second phase comparator(43) compares a negative reference clock with the phase of a feedback clock. A phase information selecting unit(45) generates a phase information signal. A variable delayer varies the amount of delay of the positive reference clock. A delay model unit(44) delays the output clock of the variable delayer. |
