METHOD FOR MANUFACTURING OF POWER SEMICONDUCTOR DEVICE
摘要
<p>PURPOSE: A method for a power semiconductor device is provided to improve the conduction loss of the semiconductor device by applying a self aligning process in order to reduce the channel resistance. CONSTITUTION: A gate insulating layer is formed on a first conductive semiconductor substrate. A gate electrode is formed at the pre-set region of the gate insulating layer. Second conductive dopant is implanted to the front side of the semiconductor substrate in order to form a second conductive well region in the surface of the semiconductor substrate. A source region is formed in the surface of the semiconductor substrate in which the second conductive well region is formed. A source electrode and a drain electrode are formed respectively in the upper side and the rear side of the semiconductor substrate.</p>
申请公布号
KR20110002601(A)
申请公布日期
2011.01.10
申请号
KR20090060142
申请日期
2009.07.02
申请人
TRINNO TECHNOLOGY
发明人
OH, KWANG HOON;KIM, EUN TAEK;YUN, CHONG MAN;LEE, JONG HUN;JUNG, JIN YOUNG