发明名称 Information processing device, processor, processor control method, information processing device control method and cache memory
摘要 In a method for controlling a processor which accesses information of a storage device through cache memory, when reading information stored in a target address or an address range of the storage device, it is monitored whether there is an update access to the address or address range from another processor, and also the processor is entered into a suspense status, which is released using the occurrence of the update access to the storage device from another processor as a trigger.
申请公布号 US7853756(B2) 申请公布日期 2010.12.14
申请号 US20040937253 申请日期 2004.09.10
申请人 FUJITSU LIMITED 发明人 UKAI MASAKI
分类号 G06F13/00;G06F1/32;G06F9/30;G06F9/312;G06F9/34;G06F9/38;G06F9/46;G06F9/52;G06F12/08;G06F15/16;G06F15/177 主分类号 G06F13/00
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