发明名称 |
Modular binary multiplier for signed and unsigned operands of variable widths |
摘要 |
A system for binary multiplication in a superscalar processor includes a first pipeline, an execution unit, and a first multiplexer; a first rotator in communication with one register of the first pipeline and the execution unit; and a leading zero detection register in communication with the execution unit and another register of the first pipeline; a second pipeline, a second execution unit, and a second multiplexer; a rotator in communication with one register of the second pipeline and the second execution unit; and a leading zero detection register in communication with the second execution unit and another register of the first pipeline; and a third pipeline, a binary multiplier in communication with a pair registers of the third pipeline; a general register; an operand buffer for obtaining first and second operands; and a bus for communication between the pipelines, the general register and the operand buffer.
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申请公布号 |
US7853635(B2) |
申请公布日期 |
2010.12.14 |
申请号 |
US20070749224 |
申请日期 |
2007.05.16 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BUSABA FADI Y.;CARLOUGH STEVEN R.;HUTTON DAVID S.;KRYGOWSKI CHRISTOPHER A.;RELL, JR. JOHN G.;VENERACION SHERYLL H. |
分类号 |
G06F7/38;G06F7/53;G06F7/52;G06F7/533;G06F9/302;G06F9/44 |
主分类号 |
G06F7/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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