发明名称 |
Parallel testing in a per-pin hardware architecture platform |
摘要 |
Provided is a method and system for testing a DUT. The system includes a plurality of testing devices for interacting with the DUT and conducting a plurality of different tests on the DUT, and a computer-readable memory for storing computer-executable instructions defining the plurality of tests to be conducted by the testing device on the DUT. A scheduler component designates at least a first test and a second test from the plurality of tests to be conducted on the DUT in parallel, wherein said designating is based at least in part on content of the computer-executable instructions defining the first test and the second test. And a controller initiates the first test and the second test to be conducted in parallel and initiating at least a third test sequentially relative to at least one of the first and second tests.
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申请公布号 |
US7853425(B1) |
申请公布日期 |
2010.12.14 |
申请号 |
US20080171765 |
申请日期 |
2008.07.11 |
申请人 |
KEITHLEY INSTRUMENTS, INC. |
发明人 |
WILLIAMSON JEROLD A.;CHAO MICHAEL;FURIO JOSEPH N.;LEI MIAO |
分类号 |
G01R31/28;G06F11/263 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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