发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 <p><P>PROBLEM TO BE SOLVED: To reduce the burden of eliminating duplication in processes for a plurality of interruption factors. <P>SOLUTION: Data transfer to an external memory 7 is complete, and data transfer completion interrupt with high priority is generated. If the data transfer of a predetermined number of packets has not completed during interruption of receiving, timer interrupt with low priority is generated. The number of transfer packets is obtained from a counter 114 before data processing of the external memory having responded to the interrupt. After resuming receiving, the counter stores the number of transfer resuming packets. After acquisition 18D of the number of transfer packets from the counter having responded to the timer interruption generation 18C, the data transfer completion interrupt 18E is generated. According to the number of obtained transfer packets, execution of either a process 18I (Fig.18(A)) to respond to the timer interrupt generation 18C or a process 18G (Fig.18(B)) to respond to the data transfer completion interrupt generation 18E is omitted. <P>COPYRIGHT: (C)2011,JPO&INPIT</p>
申请公布号 JP2010277434(A) 申请公布日期 2010.12.09
申请号 JP20090130939 申请日期 2009.05.29
申请人 RENESAS ELECTRONICS CORP 发明人 ABE HIROSHIGE;MOCHIZUKI ISAMU;MIZUTANI MIKA
分类号 G06F13/32;G06F13/28;H04B1/16;H04N5/76;H04N7/173;H04N21/426;H04N21/4385;H04N21/443 主分类号 G06F13/32
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