| 摘要 |
<P>PROBLEM TO BE SOLVED: To prevent write disturb and read disturb even when a static noise margin is small. <P>SOLUTION: A memory cell of an SRAM includes a pair of drive transistors D1 and D2, a pair of load transistors L1 and L2, a pair of write-only transmission transistors WT1 and WT2, a pair of read-only transmission transistors RT1 and RT2, a pair of read-only drive transistors RD1 and RD2, and a pair of column selection transistor CT1 and CT2, and also includes a word line WL, a pair of bit lines WBL and WBLB for writing, a pair of bit lines RBL and RBLB for reading, and a column selection line CSL. <P>COPYRIGHT: (C)2011,JPO&INPIT |
