| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide an information processing system that reduces a reduction in data processing speed due to initial access latency, while preventing unnecessary wasteful memory access. <P>SOLUTION: The information processing system includes: a master module that outputs a transfer state signal when outputting a plurality of consecutive data read instructions, and indicates that at least one data read instruction follows a certain data read instruction; and a memory controller that, when receiving the certain data read instruction and the transfer state signal from the master module, responds to the transfer state signal, reads data corresponding to at least one data read instruction following the certain data read instruction from a memory, and retains the data, while supplying the data corresponding to the certain data read instruction to the master module. <P>COPYRIGHT: (C)2011,JPO&INPIT</p> |
