| 摘要 |
PROBLEM TO BE SOLVED: To reduce power consumption in a scan test of a semiconductor integrated circuit. SOLUTION: The semiconductor integrated circuit includes a plurality of scan flip-flops constituting a scan chain during the scan test, and a plurality of clock gating circuits connected between a clock input and the plurality of scan flip-flops. The plurality of clock gating circuits are chain-connected in series, and gating setting data are serially input via the chain connection. Each of the plurality of clock gating circuits controls connection between the clock input and the scan flip-flops corresponding to the input gating setting data. COPYRIGHT: (C)2011,JPO&INPIT |
