发明名称 PHASE LOCKED LOOP DEVICE AND METHOD THEREOF
摘要 A phase locked loop device includes a phase detector that measures a difference in phase between a reference clock signal and an output clock signal provided to a device module. The phase detector provides a pulse having a width indicative of the phase difference. If the phase difference exceeds one of a plurality of threshold values, in indicator can be asserted. Based on the indicator, a control module can take remedial action, such as providing a different clock signal to the device module or triggering an interrupt at a processor device.
申请公布号 US2010310030(A1) 申请公布日期 2010.12.09
申请号 US20090480344 申请日期 2009.06.08
申请人 FREESCALE SEMICONDUCTOR, INC. 发明人 BHAGAVATHEESWARAN GAYATHRI A.;GERGEN JOSEPH P.;RAMAN ARVIND;SANCHEZ HECTOR
分类号 H03D3/24 主分类号 H03D3/24
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