| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a test condition adjustment device and a test condition adjustment method, for preventing the increase of the scale of a chip. <P>SOLUTION: A comparison part 2 compares voltage drop under first operation conditions with voltage drop under second operation conditions in a semiconductor circuit to be designed, for example by performing simulation. In this case, the first operation conditions are, for example, operation conditions in actual operation after a semiconductor circuit is completed, and the second operation conditions are, for example, operation conditions when performing a shipping test (in a test) after the semiconductor circuit is completed. An adjustment part 3 adjusts the second operation conditions based on the delay characteristics of the semiconductor circuit when the voltage drop under the second operation conditions is larger than voltage drop under the first operation conditions. <P>COPYRIGHT: (C)2011,JPO&INPIT</p> |
