| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a PLL (Phase-Locked Loop) circuit where low power consumption and miniaturization are both achieved. <P>SOLUTION: A phase comparator 2 at the PLL circuit includes a counter 16 and a time digital converter 13. The counter 16 receives a reference clock signal REF, a low frequency clock signal CLKA, obtained by frequency division of the output of a digitally controlled oscillator, and a high frequency clock signal CLKB. The counter 16 counts the clock number of the high frequency clock signal CLKB to detect phase difference between the reference clock signal REF and the low frequency clock signal CLKA. The time digital converter 13 receives the reference clock signal REF and the low frequency clock signal CLKA. The time digital converter 13 detects the phase difference between the reference clock signal REF and the low frequency clock signal CLKA in accuracy of a time period shorter than the period of the high frequency clock signal CLKB, after the output of the counter 16 enters into a predetermined range. <P>COPYRIGHT: (C)2011,JPO&INPIT |
