| 摘要 |
An object of the present invention is to provide a DLL circuit adjustment system that can adjust the sampling timing of a DLL circuit without causing any increase of the number of interface signals or amount of coding overhead and any reduction of the data transfer efficiency. On a transmitter side, an ECC generating section adds an error detection/correction code to transmission data and outputs the transmission data with the error detection/correction code. Of output channels of the transmission data from the ECC generating section, a data bit associated with the DLL circuit to be adjusted is replaced with a sampling timing adjustment pattern using a to-be-adjusted channel selection circuit and a selector, and the resulting transmission data is transmitted to a receiver side. On the receiver side, the transmission data is received via a DLL circuit provided for each channel of the received transmission data, and an error detecting/correcting section corrects any error in the output of each DLL circuit, thereby forming received data. In this way, normal data transfer can be maintained while adjusting the sampling timing of each DLL circuit.
|
