| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device securing a sufficient time margin between aligned data and data input strobe signals, and latching the aligned data by controlling the timing of activation of a latch control signal according to an operation mode. <P>SOLUTION: The semiconductor memory device comprises: a data alignment part for aligning a plurality of data items inputted sequentially, in response to a data strobe signal; a latch operation control part for receiving the data strobe signal, and generating a latch control signal in response to information indicating an interval between one write operation and the next write operation; a data latch part for latching an output signal of the data alignment part in response to the latch control signal; and a data synchronization output part for synchronizing output signals of the data latch part in response to a data input strobe signal, and outputting them to a plurality of global data lines. <P>COPYRIGHT: (C)2012,JPO&INPIT |
