Transaction based verification of a system on chip on system level by translating transactions into machine code

摘要

In a transaction-based verification environment for complex semiconductor devices, enhanced verification efficiency may be achieved by providing a transaction to machine code translator and an appropriate interface that enables access of the translated machine code instruction by a CPU under test. In this manner, transaction-based test environments may have a high degree of re-usability and may be used for verification on block level and system level.