发明名称 LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME
摘要 <P>PROBLEM TO BE SOLVED: To provide a layered chip package that facilitates implementing a package that provides, even if it includes a malfunctioning semiconductor chip, the same functions as those for the case where no malfunctioning semiconductor chip is included. <P>SOLUTION: A layered chip package 1A, 1B includes a main body 2, and wiring 3 disposed on a side surface of the main body 2. The main body 2 includes: a main part 2M including a plurality of layer portions; a plurality of first terminals 4 disposed on the top surface of the main part 2M and connected to the wiring; and a plurality of second terminals disposed on the bottom surface of the main part 2M and connected to the wiring. The plurality of layer portions include a first-type layer portion 10A and a second-type layer portion 10B. The first-type layer portion 10A includes a conforming semiconductor chip, and a plurality of first-type electrodes that are connected to the semiconductor chip and the wiring. The second-type layer portion 10B includes a defective semiconductor chip, and a plurality of second-type electrodes that are connected to the wiring and not to the semiconductor chip. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012009807(A) 申请公布日期 2012.01.12
申请号 JP20100288172 申请日期 2010.12.24
申请人 HEADWAY TECHNOLOGIES INC;SAE MAGNETICS (HK) LTD 发明人 SASAKI YOSHITAKA;ITO HIROYUKI;IKEJIMA HIROSHI;IIJIMA ATSUSHI
分类号 H01L25/065;H01L25/07;H01L25/18 主分类号 H01L25/065
代理机构 代理人
主权项
地址
您可能感兴趣的专利