发明名称 MEMORY DEVICE AND CPU CONTROL METHOD
摘要 <P>PROBLEM TO BE SOLVED: To correctly obtain a chip-specific write and erase times. <P>SOLUTION: A memory 102 comprises: a pulse counter 106a for counting, during an actual rewrite operation, the number of applications of a predetermined voltage pulse required for the rewrite operation; a pulse count storage register 106b for storing the number of applications of the predetermined voltage pulse, which is counted by the pulse counter 106a; and a required time output part 107 for outputting data indicating a time required for the write operation on the basis of the number of applications stored in the pulse count storage register 106b. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012027964(A) 申请公布日期 2012.02.09
申请号 JP20100163079 申请日期 2010.07.20
申请人 PANASONIC CORP 发明人 NISHIKAWA KAZUYO;NOICHI SHIYUUHEI;ARITA MEI;KATO JUNICHI;MIYOSHI ASAKO
分类号 G11C16/02;G11C16/06 主分类号 G11C16/02
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