| 摘要 |
U.S. Pat. No. 3,684,920 issued on Aug. 15, 1972 and based on U.S. Patent Application Serial No. 37,668, filed May 15, 1970, describes a transistor deflection circuit employing an output stage of class B, push-pull complementary symmetry type and a Miller integrator approach for the sawtooth wave generation. This invention describes a modification to the discharge circuitry thereof to improve the vertical deflection stability in the presence of spurious pulses which tend to undesirably and randomly trigger and/or retrigger the discharge switch. An additional "blanker" transistor is employed to sense the voltage across the vertical yoke winding so as to bypass the spurious signals away from the discharge switch during the vertical retrace interval when the danger exists that the deflection circuits will be falsely triggered.
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