| 摘要 |
<P>PROBLEM TO BE SOLVED: To shorten the lockup time of a PLL circuit. <P>SOLUTION: A phase comparator 10 compares a phase of an input clock to a PLL circuit 100 with a phase of a feedback clock fed back from an output of the PLL circuit 100 via a frequency divider 40, and generates a signal depending on a resultant phase difference. An LPF 20 generates a DC voltage depending on an output signal of the phase comparator 10. A voltage-controlled oscillator 30 outputs a clock of a frequency depending on the voltage generated by the LPF 20. A cycle slip prediction circuit 50 monitors the signal generated by the phase comparator 10 to predict the occurrence of a cycle slip. When the cycle slip prediction circuit 50 predicts the occurrence of a cycle slip, any one of the phase of the input clock, the phase of the feedback clock and the voltage input into the voltage-controlled oscillator is adjusted. <P>COPYRIGHT: (C)2012,JPO&INPIT |
