发明名称 SIGNAL WIRING SYSTEM AND JITTER SUPPRESSION CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To solve the conventional problem of difficulty in suppressing an increase in a circuit scale while reducing the amount of jitter in signal wiring. <P>SOLUTION: A signal wiring system comprises: an output unit that outputs a differential signal; a reception unit that receives the differential signal from the output unit; a jitter suppression circuit that suppresses the amount of jitter in the differential signal received by the reception unit according to a suppression coefficient; and a signal wiring unit that transmits the differential signal from the output unit, and has a wiring length corresponding to the suppression coefficient in the jitter suppression circuit. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012182709(A) 申请公布日期 2012.09.20
申请号 JP20110044895 申请日期 2011.03.02
申请人 RENESAS ELECTRONICS CORP 发明人 AOKI YASUSHI
分类号 H04L7/02;H04L25/02 主分类号 H04L7/02
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