| 摘要 |
<P>PROBLEM TO BE SOLVED: To achieve both miniaturization and reduction in an output capacitance simultaneously. <P>SOLUTION: In a conventional semiconductor device, depths of a drain region and a source region are shallower (thinner) than a thickness of an active layer. On the contrary, in a semiconductor device 1 according to the embodiment, a thickness of an active layer 3 is thinned so as to equalize the depths of drain regions 4A and 4B and source regions 5A and 5B with the thickness of the active layer 3. As a result, since a junction area of a PN junction between the N-type drain regions 4A and 4B and source regions 5A and 5B and P-type base regions 7A and 7B is reduced compared with the conventional art, an output capacitance Coss generated at the PN junction can be reduced. In addition, since two diodes and a wiring pattern can be eliminated compared with the conventional art described in a patent literature 1, the device can be miniaturized. <P>COPYRIGHT: (C)2012,JPO&INPIT |
