| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a false lock prevention circuit and a method which are used to cause a delayed locked loop to escape from false lock, when the false lock has occurred in the delayed locked loop, and also provide a delayed locked loop using the same. <P>SOLUTION: The false lock prevention circuit includes a detector configured to detect harmonic lock and a detector configured to detect stuck lock. The harmonic lock detector includes: a plurality of flip-flops configured to sample a plurality of delayed clocks with a characteristic method of this invention; and a logic unit. The harmonic lock detector compares the positive edge of a reference clock with the positive edges of the plurality of delayed clocks delayed from the reference clock, and detects whether or not the positive edges deviate from one cycle of the reference clock. The stuck lock detector is a logic circuit utilizing an output signal of a phase detector and one of the delayed clocks, and causes the phase detector to be reset depending on a result of a logic operation. <P>COPYRIGHT: (C)2013,JPO&INPIT |
