| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a transceiver supplied with transmission data asynchronously to a clock used for sampling, capable of correct sampling of transmission data signal level. <P>SOLUTION: When a start edge timing (a start timing) of transmission data TXD start bit is detected, the transceiver samples the transmission data TXD at the time of second sampling edge after the start timing using a sampling SCK having four sampling edges per one bus clock BCK cycle after synchronizing to the bus clock BCK, and afterwards, samples (latches) the transmission data TXD at every four sampling edge timing. The transceiver generates synchronous transmission data dTXD synchronized to the bus clock BCK by additionally sampling the sampled data at the time of falling edge of the bus clock BCK. <P>COPYRIGHT: (C)2013,JPO&INPIT |
