发明名称 SEMICONDUCTOR CHIP AND MANUFACTURING METHOD THEREOF AND SEMICONDUCTOR PACKAGE
摘要 <P>PROBLEM TO BE SOLVED: To execute wafer test appropriately before rewiring is formed. <P>SOLUTION: A semiconductor chip 1 comprises: a first rewiring connection part 61 which is located inside a peripheral electrode pad 30 or a position relatively near the peripheral electrode pad 30 in a V/G wiring 20; and a second rewiring connection part 62 which is located at a position relatively far from the peripheral electrode pad 30 in the V/G wiring 20 and whose potential before formation of a rewiring 60 is smaller than that of the first rewiring connection part 61, the first rewiring connection part 61 and the second rewiring connection part 62 being connected together by the rewiring 60. The semiconductor chip 1 is provided with an inspection part 80 for wafer test in the second rewiring connection part 62, a portion near the second rewiring connection part 62 on the V/G wiring 20 whose potential before formation of the rewiring 60 is smaller than that of the first rewiring connection part 61, or a conductive portion led out from the V/G wiring 20 to near the second rewiring connection part 62 and whose potential before formation of the rewiring 60 is smaller than that of the first rewiring connection part 61. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2013008742(A) 申请公布日期 2013.01.10
申请号 JP20110138711 申请日期 2011.06.22
申请人 RENESAS ELECTRONICS CORP 发明人
分类号 H01L21/66;H01L21/3205;H01L21/768;H01L23/522 主分类号 H01L21/66
代理机构 代理人
主权项
地址