| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a memory circuit in which erroneous writing is less likely to occur at the time of power-up. <P>SOLUTION: A memory circuit 10 includes a P channel type nonvolatile memory element 15 for writing into which the data is written by applying a voltage between source and drain only at the time of writing, and an N channel type nonvolatile memory element 16 having a control gate and a floating gate common to the P channel type nonvolatile memory element 15, and from which the data is read by applying a voltage between source and drain only at the time of reading. <P>COPYRIGHT: (C)2013,JPO&INPIT |
