发明名称 FAIL POINT ESTIMATION DEVICE, METHOD AND PROGRAM
摘要 <P>PROBLEM TO BE SOLVED: To provide a device and a method capable of performing fault diagnosis on the entire of a logic circuit including a function block and an additional circuit having a scan test design to largely reduce the diagnosis processing time. <P>SOLUTION: A fail point estimation device includes: circuit dividing means 2 that receives a piece of configuration information of a scan chain including scan flip-flops in a logic circuit and a piece of design information of a logic circuit as input data 1 and extracts a circuit portion other than a parallel area in the logic circuit as a serial area to divide the logic circuit into the parallel area and a serial area; estimation value calculation means 3 that calculates a logical value in a normal circuit as an estimation value; and fault diagnosis means 4 that receives a test output on a test pattern from the logic circuit as the input data 1 and performs a fault diagnosis on the parallel area and the serial area using the test output and the estimation value of the serial area and the parallel area to output the result to an output section. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2013019744(A) 申请公布日期 2013.01.31
申请号 JP20110152725 申请日期 2011.07.11
申请人 RENESAS ELECTRONICS CORP 发明人 SEIYAMA TETSUYA
分类号 G01R31/28;G06F11/22 主分类号 G01R31/28
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