| 摘要 |
<P>PROBLEM TO BE SOLVED: To avoid occurrence of violation of hold to a user logic path between different clock domains in a scan test. <P>SOLUTION: First scan flip-flops (111/112) are included in first clock domains (101/102) operating in response to first clock signals (CLK1/CLK2) and assembled in a scan chain formed at the scan test. Hold corresponding circuits (202/201) belong to second clock domains (102/101) operating in response to second clock signals (CLK2/CLK1) having the frequency different from that of the first clock signals (CLK1/CLK2) and fix data outputting to the first scan flip-flops (111/112) in a capture period for fetching a test result to the scan chain. At the scan test, clock signals of same frequency are supplied to the first clock domain and second clock domain (101, 102). <P>COPYRIGHT: (C)2013,JPO&INPIT |
