| 摘要 |
<P>PROBLEM TO BE SOLVED: To enable easy obtainment of information on memory access needed for evaluating performance of a data processing device such as a system LSI, at actual machine evaluation. <P>SOLUTION: A CPU 110 controls a whole system. Access to common memory 105 is performed from a plurality of bus masters through a system bus 111. A bus arbiter 112 arbitrates data transfer from each bus master to the system bus 111. A clock generation circuit 113 supplies a clock signal to each part. A memory control circuit 120 has a command generation circuit 124 for executing a memory access request from a bus master. A monitor 126 acquires the memory access request and information on an execution cycle, and the information is held by a trace-cue 127, and written in the memory 105 as execution history information by a data writing circuit 128. A changeover circuit 129 switches the output of the command generation circuit 124 and the output of the data writing circuit 128, and outputs to the memory 105. <P>COPYRIGHT: (C)2013,JPO&INPIT |
