Phase detector circuit for clock and data recovery circuit and optical communication device having the same

摘要

A high-accuracy phase detector circuit compatible with a 1/N rate architecture is provided. The phase detector circuit has as many as N track-and-hold circuits for tracking and holding N-phase clock signals CLK-1 to CLK_N in synchronization with a rising edge of input data signal DIN. Out of the N-phase clock signals CLK-1 to CLK_N outputted from as many track-and-hold circuits, only the one whose rising edge is most synchronized with a rising edge of the input data signal DIN is selected and outputted as a phase difference signal.