发明名称 |
SPIN TRANSISTOR AND MEMORY |
摘要 |
PROBLEM TO BE SOLVED: To provide a spin transistor which has an S value of 60 mV/decade or less and which can inhibit decrease in I/Iratio when a finite bias is applied.SOLUTION: A spin transistor according to a present embodiment comprises: a semiconductor layer including a pregion and an nregion which are arranged away from each other and an i region provided between the pregion and the nregion; a first electrode which is provided on the pregion and includes a first ferromagnetic layer; a second electrode which is provided on the nregion and includes a second ferromagnetic layer; and a gate provided on the i region. |
申请公布号 |
JP2013201386(A) |
申请公布日期 |
2013.10.03 |
申请号 |
JP20120070144 |
申请日期 |
2012.03.26 |
申请人 |
TOSHIBA CORP |
发明人 |
IGUCHI TOMOAKI;ISHIKAWA MIZUE;SUGIYAMA HIDEYUKI;SAITO YOSHIAKI |
分类号 |
H01L29/82;H01L21/8246;H01L27/105 |
主分类号 |
H01L29/82 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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