| 摘要 |
PROBLEM TO BE SOLVED: To provide a delay circuit that can produce a desired delay time even if using inverters involving variations due to temperature, supply voltage and process conditions.SOLUTION: A first delay generation section 10 comprises N inverters 1[1]-1[N] (N is a natural number) connected in series. AND circuits 2[1]-2[8], D flip-flops 3[1]-3[8] and D flip-flops 4[1]-4[8] detect synchronization between outputs of eight inverters 1 from the 600th to the 2,000th of the first delay generation section 10 and a clock signal CLK. In accordance with the number of stages of the inverters 1[1]-1[N] where synchronization is detected, a decoder circuit 5 instructs a selector circuit 6 to select as an output signal a signal at an output node of any one stage of M inverters 8[1]-8[M] (M is a natural number satisfying N>M) connected in series in a second delay generation section 30. |
