Transparent level 2 cache that uses independent tag and valid random access memory arrays for cache access

摘要

A system comprising a processor, a first cache, and a second cache. The processor is configured to perform a processing task according to data stored in a main memory and output a command associated with the processing task. The first cache is located between the processor and the main memory and is configured to store a first portion of the data stored in the main memory and provide a first indication of whether the command has been completed at the first cache. The second cache is located between the first cache and the main memory and is configured to store a second portion of the data stored in the main memory and provide a second indication of whether the command has been completed at the second cache. The processor is configured to perform the processing task in response to receiving both the first indication and the second indication.