| 摘要 |
A procedure for obtaining noise temperatures of a field effect transistor (FET) embedded on a wafer through an analytical procedure which processes measured noise figure data over transistor's size Pd within a frequency range at constant voltage and current density. The parasitic elements associated with an electrical model of the embedding structures are determined. Then, for each of n=1, 2, . . . N FETs, the scattering parameters and noise figure Fmeas,n are measured, the components of the core model, normalized to the periphery Pd are determined, and the noise contributions of the parasitic components are de-embedded from Fmeas,n. The noise temperatures tgs, tds, and tgd are found by solving the equation 4 N i G s ( F meas , n - 1 ) - y s + C T A y s - y s + T B , n T A C T C T A + T B , n + y s P d n = A n t ds + B n t gs + C n t gd using at least three values of Fmeas,n and Pd,n. Finally, the noise temperatures Tgs, Tds, and Tgd are found, where Tgs=tgs*T0, T0=290K; Tds=tds*T0; and Tgd=tgd*T0. |
