| 摘要 |
<p>The memory device comprises: a series string of memory cells; a current sensing circuit coupled to a bit line of the series string of memory cells and configured to generate a sense amplifier control signal in response to detection of a bit line current generated by a read threshold voltage on a word line of the series string of memory cells; a voltage generator coupled to the word line and configured to generate a ramped voltage on which the read threshold voltage is located; and a sample/hold and comparator circuit (802) coupled to the bit line, the circuit comprising: a first capacitor (813) coupled to the voltage generator through a first switch (810) and configured to store a representation of the read threshold voltage; a first operational amplifier-driver (820) coupled to the first capacitor (813) and configured to output data representative of the read threshold voltage; a second capacitor (805) coupled to the voltage generator through a second switch (806) and configured to store a representation of a target threshold voltage; and a second operational amplifier-driver (807) coupled to the second capacitor (805) and to the output of the first operational amplifier driver (820), the second operational amplifier-driver (807) configured to generate an inhibit signal in response to the sense amplifier control signal and a comparison of the representation of the read threshold voltage with the representation of the target voltage.</p> |
