发明名称
摘要 <p><P>PROBLEM TO BE SOLVED: To provide an error correction circuit, a memory device, and an error correction method which can perform error correction at high-speed and suppress an increase in structure and/or power consumption of the error correction circuit. <P>SOLUTION: An error correction circuit comprises: input means 153 for inputting an odd number of pieces of redundant binary information in current values; conversion means 151 for converting the sum of the odd number of current values input via the input means into voltage; and first determination means 152 for outputting binary information according to whether the voltage output by the conversion means is equal to or more than a first preset threshold. <P>COPYRIGHT: (C)2013,JPO&INPIT</p>
申请公布号 JP5502003(B2) 申请公布日期 2014.05.28
申请号 JP20110060500 申请日期 2011.03.18
申请人 发明人
分类号 G06F12/16;G11C11/41;G11C16/02;H03M13/43 主分类号 G06F12/16
代理机构 代理人
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