REDUCING POWER GRID NOISE IN A PROCESSOR WHILE MINIMIZING PERFORMANCE LOSS

摘要

In the management of a processor, logical operation activity is monitored for increases from a low level to a high level during a sampling window across multiple cores sharing a common supply rail, with at least one decoupling capacitor along the common supply rail. Responsive to detecting the increase in logical operation activity from the low level to the high level during the sampling window, the processor limits the logical operations executed on the cores during a lower activity period to a level of logical operations set between the low level and a medium level, where the medium level is an amount between the low level and the high level. Responsive to the lower activity period ending, the processor gradually decreases the limit on the logical operations to resume normal operations.

主权项

1. A method for managing a processor, comprising:
monitoring, by a processor, for an increase in logical operation activity from a low level to a high level during a sampling window across a plurality of cores sharing a common supply rail of the processor; responsive to the processor detecting the increase in logical operation activity from the low level to the high level during the sampling window, limiting, by the processor, the logical operations executed on the plurality of cores during a lower activity period to a level of logical operations set between the low level and a medium level, where the medium level is an amount between the low level and the high level; and responsive to the lower activity period ending, gradually decreasing, by the processor, the limit on the logical operations executed on the plurality of cores to resume normal operations.