| 摘要 |
PROBLEM TO BE SOLVED: To reduce global steps in a wiring layer on an upper layer side of a multilayer wiring layer.SOLUTION: A semiconductor device 1 includes a multilayer wiring layer 5 in which wiring layers 51-55 are stacked, on a semiconductor substrate 2. A step for forming respective wiring layers 51-55 includes a wiring formation step for forming actual wirings 61R-65R and dummy wirings 61D-65D, an insulation film formation step for forming insulation films 71-75 which cover them, and a flattening step for flattening surfaces of the insulation films 71-75. The manufacturing method includes a non-dummy in-plane distribution calculation step which acquires, by calculation, an in-plane distribution of entire layer thickness of a multilayer wiring layer 5 in a case where, with no dummy wiring being formed, the wiring formation step, the insulation film formation step, and the flattening step are performed to form respective wiring layers, and a region setting step which, based on the in-plane distribution of the entire layer thickness, sets a dummy arrangement region 11 and a dummy non arrangement region 12. The dummy wirings 61D-65D are formed in the dummy arrangement region 11 by detouring the dummy non arrangement region 12. |
