发明名称 設定可能なデジタル−アナログ位相ロックループ
摘要 <p>A phase locked loop (PLL) device is configurable in an analog phase locked loop and a hybrid analog-digital phase locked loop. In an analog mode, at least a phase detector, an analog loop filter, and a voltage controlled oscillator (VCO), are connected to form an analog loop. In a digital mode, at least the phase detector, the voltage controlled oscillator (VCO), a time to digital converter (TDC), a digital loop filter and a digital to analog converter (DAC) are connected to form the hybrid digital-analog loop.</p>
申请公布号 JP5661793(B2) 申请公布日期 2015.01.28
申请号 JP20120543215 申请日期 2010.12.07
申请人 发明人
分类号 H03L7/22;H03L7/093 主分类号 H03L7/22
代理机构 代理人
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