| 发明名称 |
MEMORY DEVICE, MEMORY SYSTEM, AND METHOD OF CONTROLLING READ VOLTAGE OF THE MEMORY DEVICE |
| 摘要 |
A memory device includes a memory cell array having a plurality of memory cells, and a page buffer unit including a plurality of page buffers configured to store a plurality of pieces of data sequentially read from some of the plurality of memory cells at different read voltage levels, respectively, and to perform a logic operation on the plurality of pieces of data, respectively. The memory device further includes a counting unit configured to count the number of memory cells that exist in each of a plurality of sections defined by the different read voltage levels, based on results of the logic operation |
| 申请公布号 |
US2015029796(A1) |
申请公布日期 |
2015.01.29 |
| 申请号 |
US201313948557 |
申请日期 |
2013.07.23 |
| 申请人 |
CHOI MYUNG-HOON;JEONG JAE-YONG;PARK KI-TAE |
发明人 |
CHOI MYUNG-HOON;JEONG JAE-YONG;PARK KI-TAE |
| 分类号 |
G11C7/10;G11C29/44 |
主分类号 |
G11C7/10 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A memory device comprising:
a memory cell array comprising a plurality of memory cells; a page buffer unit comprising a plurality of page buffers configured to store a plurality of pieces of data sequentially read from some of the plurality of memory cells at different read voltage levels, respectively, and to perform a logic operation on the plurality of pieces of data, respectively; and a counting unit configured to count the number of memory cells that exist in each of a plurality of sections defined by the different read voltage levels, based on results of the logic operation. |
| 地址 |
SUWON-SI KR |
