SINGLE WIRE SERIAL INTERFACE

摘要

A single wire serial interface for power ICs and other devices is provided. To use the interface, a device is configured to include an EN/SET input pin. A counter within the device counts clock pulses sent to the EN/SET input pin. The output of the counter is passed to a ROM or other decoder circuit. The ROM selects an operational state for the device that corresponds to the value of the counter. In this way, control states may be selected for the device by sending corresponding clock pulses to the EN/SET pin. Holding the EN/SET pin high causes the device to maintain its operational state. Holding the EN/SET pin low for a predetermined timeout period resets the counter and causes the device to adopt a predetermined configuration (such as off) until new clock pulses are received at the EN/SET pin.

主权项

1. A power integrated circuit device having at least one input and at least one output, comprising:
a core circuit that produces the at least one output of the power integrated circuit; and an interface in communication with the core circuit, the interface including (i) counter circuitry that generates a count value based on pulses encoded in an input signal received via a single input of the power integrated circuit, (ii) latch driver circuitry that asserts a latch signal when the input signal is maintained high for a period that exceeds a predetermined latch timeout value, (iii) a latch that stores the count value based on the latch signal being asserted, (iv) decoder circuitry that associates the count value in the latch with a corresponding lighting control state that is communicated to a light source via the at least one output, and (v) sensing circuitry that determines whether the input signal is high or low so that the count value is maintained while the input signal is high, and the count value is reset in response to the input signal being low for a period that exceeds a predetermined timeout value, the predetermined timeout value being longer than a width of one of the pulses.