WIDE RANGE MULTIPORT BITCELL

摘要

A multiport bitcell including a pair of cross-coupled inverters is provided with increased write speed and enhanced operating voltage range by the selective isolation of a first one of the cross-coupled inverters from a power supply and ground during a write operation. The write operation occurs through a write port that includes a transmission gate configured to couple a first node driven by the first cross-coupled inverter to a write bit line. A remaining second cross-coupled inverter in the bitcell is configured to drive a second node that couples to a plurality of read ports.

主权项

1. A circuit for a memory cell, comprising:
a pair of cross-coupled inverters, wherein a first inverter in the pair is configured to drive a first node for the memory cell and a remaining second inverter in the pair is configured to drive a second node for the memory cell; a plurality of read ports configured to access the second node; a first write port including a write word line, a complement write word line, and a write bit line; a first transmission gate configured to couple the first node to the write bit line responsive to an assertion of the write word line and the complement write word line; and a power switch configured to isolate the first inverter from a power supply responsive to the assertion of the write word line,