| 发明名称 |
SIGNAL CONTROL CIRCUIT, INFORMATION PROCESSING APPARATUS, AND DUTY RATIO CALCULATION METHOD |
| 摘要 |
A signal control circuit includes: a delay acquisition circuit configured to obtain a first delay amount to be added to an input signal for aligning timing of rise of the input signal with timing of fall or rise of a reference signal and a second delay amount to be added to the input signal for aligning timing of fall of the input signal with timing of the fall or the rise of the reference signal; and a ratio calculation circuit configured to calculate a duty ratio of the input signal based on a difference between the first delay amount and the second delay amount. |
| 申请公布号 |
US2015032950(A1) |
申请公布日期 |
2015.01.29 |
| 申请号 |
US201414296965 |
申请日期 |
2014.06.05 |
| 申请人 |
FUJITSU LIMITED |
发明人 |
Ookubo Katsuhiko;Hashimoto Michitaka;Tokuhiro Noriyuki |
| 分类号 |
G11C7/22;G11C7/10 |
主分类号 |
G11C7/22 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A signal control circuit, comprising:
a delay acquisition circuit configured to obtain a first delay amount to be added to an input signal for aligning timing of rise of the input signal with timing of fall or rise of a reference signal and a second delay amount to be added to the input signal for aligning timing of fall of the input signal with timing of the fall or the rise of the reference signal; and a ratio calculation circuit configured to calculate a duty ratio of the input signal based on a difference between the first delay amount and the second delay amount. |
| 地址 |
Kawasaki-shi JP |
