发明名称 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
摘要 Embodiments of the inventive concept include a semiconductor package having a plurality of stacked semiconductor chips. A multi-layered substrate includes a central insulation layer, an upper wiring layer disposed on an upper surface of the central insulation layer, and a first lower wiring layer disposed on a lower surface of the central insulation layer. The stacked semiconductor chips are connected to the multi-layered substrate and/or each other using various means. The semiconductor package is capable of high performance operation, like a semiconductor package based on flip-ship bonding, and also meets the need for large capacity by overcoming a limitation caused by a single semiconductor chip. Embodiments of the inventive concept also include methods of manufacturing the semiconductor package.
申请公布号 US2015028474(A1) 申请公布日期 2015.01.29
申请号 US201414328668 申请日期 2014.07.10
申请人 JANG Chul-yong;KIM Young-lyong;JANG Ae-nee 发明人 JANG Chul-yong;KIM Young-lyong;JANG Ae-nee
分类号 H01L23/498;H01L23/522 主分类号 H01L23/498
代理机构 代理人
主权项 1. A semiconductor package comprising: a multi-layered substrate comprising a central insulation layer, an upper wiring layer disposed on an upper surface of the central insulation layer, and a first lower wiring layer disposed on a lower surface of the central insulation layer; a first semiconductor chip disposed on the upper wiring layer and connected to buried lower pads of the first lower wiring layer via penetrating bumps that penetrate through the upper wiring layer and the central insulation layer; and a second semiconductor chip stacked on the first semiconductor chip in an offset structure such that the second semiconductor chip protrudes horizontally from the first semiconductor chip, the second semiconductor chip connected to upper pads of the upper wiring layer via upper bumps.
地址 Hwaseong-si KR