发明名称 SYSTEM VERIFICATION SUPPORT APPARATUS
摘要 PROBLEM TO BE SOLVED: To provide a system verification support apparatus capable of performing a formal verification on a distribution system for accurately performing asymmetrical iterative calculation while reducing a calculation amount.SOLUTION: A system verification support apparatus according to an embodiment of the present invention comprises: a formal verification unit 22 that is intended to verify a system configured by a plurality of nodes and links connecting these plural nodes, and that performs image calculation of an attainment state set of the nodes for each of the nodes on the basis of an initial state set of the nodes, a transition relation among the nodes, and the attainment state set of the plural nodes; and an output unit 23 that outputs the attainment state set obtained by the image calculation.
申请公布号 JP2015018498(A) 申请公布日期 2015.01.29
申请号 JP20130146683 申请日期 2013.07.12
申请人 TOSHIBA CORP 发明人 SAKAI YOSHIAKI
分类号 G06F11/36;G06F11/28;G06F17/50 主分类号 G06F11/36
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