METHODS FOR OPERATING A FINFET SRAM ARRAY

摘要

A method of operating an SRAM array may include: providing a plurality of bit cells, each of the plurality of bit cells comprising a cross coupled inverter pair; a first pass gate; and a second pass gate. A word line voltage may be applied to the first pass gate and the second pass gate, while a first cell positive voltage supply CVdd may be applied to terminals of the cross coupled inverter pair. The first cell positive voltage supply CVdd may be varied relative to the word line voltage during a selected operation of the plurality of bit cells

主权项

1. A method comprising:
applying a first voltage level to a first array of SRAM cells, the SRAM cells of the first array including only single fin finFET transistors formed on a substrate, and to a second array of SRAM cells, the SRAM cells of the second array including single fin finFET transistors and multiple fin finFET transistors formed on the substrate; applying a word line voltage to a word line associated with the first array of SRAM cells; and lowering the first voltage level applied to the first array of SRAM cells to a level lower than the word line voltage during an operation to write data to the first array of SRAM cells.