| 摘要 |
<p>A liquid crystal display is provided, which can disperse the load of source drive integrated circuits by delaying timing control signals. A plurality of gate lines and a plurality of datalines are arranged to be crossed in the LCD panel(10). The memory(12) can be updated and stores the delay-value information. The timing controller(11) generates data timing control signal and the gate timing control signal. The data timing control signal includes a plurality of source output enable signals. A plurality of source output enable signals have the different delay-value. The source drive integrated circuits(131~136) convert digital video data into the analog data voltage. The gate drive integrated circuits(151~153) supply the gate pulse to the gate lines.</p> |
