| 摘要 |
The present invention relates to a shift register capable of preventing multi output. The present invention includes stages which successively output scan pulses through their output terminals. A n-th stage (n is a natural number) among the stages includes a set starting switching element which controls the voltage state of a set nod according to the set starting signal from the outside; a first pull-up switching element which is controlled by the voltage of the set node and is connected between an output clock transmission line of transmitting at least one output clock pulse and the output terminal of the n-the stage; a capacitor which is connected between a clear clock transmission line of transmitting at least one clear clock pulse and a reset node; and a clear switching element which controls the voltage state of the set node according to the voltage of the recess node. |
